1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device of an open bit line type.
2. Description of Related Art
A semiconductor memory device represented by a DRAM includes a sense amplifier connected to a pair of bit lines, and a potential difference appearing in the bit line pair is amplified by the sense amplifier. Known methods for wiring a bit line pair include a folded bit line type in which a bit line pair is wired in the same direction as viewed from a sense amplifier, and an open bit line type in which a bit line pair is wired in the opposite direction to each other as viewed from a sense amplifier.
In the folded bit line type, the pair of bit lines intersects the same word line, and thus when a word line is activated, the same coupling noise is superposed on the bit lines. Thus, the noise accompanying with the activation of the word line is cancelled. On the other hand, in the open bit line type, the pair of bit lines intersects mutually different word lines, and thus when the word line is activated, coupling noise is superposed on only one of the bit lines. Thus, an operation margin of the sense amplifier is reduced, and data can be inverted in some cases.
As a method of solving the problem in the open bit line type, there is known a method of canceling noise by using a dummy word line (see Japanese Patent Application Laid-open No. H6-103754: hereinafter referred to as “patent document 1”).
However, in the semiconductor memory device described in the above patent document 1, a dummy cell is connected to a dummy word line. Accordingly, a memory cell, which is a reading target, is connected to one of bit lines and the dummy cell is connected to the other of the bit lines. Therefore, to prevent a problem in a sense operation, it is necessary to correctly control a potential to be stored in the dummy cell. Generally, one dummy cell is shared by a large number of memory cells. Therefore, to equalize the influence exerted on memory cells in which a high level is stored and on memory cells in which a low level is stored, it is necessary to accurately set the potential to be stored in the dummy cell to an intermediate level (an intermediate potential between high level and low level). This configuration requires a circuit that produces an accurate intermediate level, and as a result, there arises a problem that the chip size is increased.
Furthermore, according to the technique of the above patent document 1, it is necessary to have, within a memory mat, an active region in which a dummy cell is formed, and this can cause a problem of increasing the chip size.